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[SCM] Digital_Clock-7Seg

Description: Digital Clock Source using ATmega8515 and 7Segment
Platform: | Size: 23552 | Author: kang | Hits:

[SCM] A_digita_clock_made_by_Microchip

Description: 本次设计中以单片机的发展过程和发展方向为背景，介绍了单片机的输入输出的工作原理和操作方法，中断的工作原理和操作方法。4511的工作原理和操作方法，LED的内部结构。电路设计及调试过程。 本次做的数字钟是以单片机（AT89C51）为核心，结合相关的元器件（共阴极LED数码显示器、BCD-锁存/7段译码/驱动器CC4511等），再配以相应的软件，达到制作简易数字钟的目的，其硬件部分难点在于元器件的选择、布局及焊接。 -The design of a single-chip development process and the development direction for the background, introduced the single-chip input and output of the working principle and method of operation, interruption of the working principle and method of operation. 4511 the working principle and method of operation, LED s internal structure. Circuit design and debugging process. To do this is based on single-chip digital clock (AT89C51) as the core, combined with related components (common cathode LED digital display, BCD-latch/7 segment decoder/driver CC4511, etc.), together with the corresponding software to create simple digital clock The purpose of the hardware part of the difficulties lies in the choice of components, layout and welding.
Platform: | Size: 1253376 | Author: thocr | Hits:

[SCM] clock-mega8_4bit-7se

Description: 4位7段数码管电子钟C语言源文件，使用ICC开发，单片机为ATmega8，详细接口定义见注释-4-digit 7-segment digital tube digital clock C language source files, use the ICC development of SCM as ATmega8, detailed interface definitions, see note
Platform: | Size: 24576 | Author: wanghao | Hits:

[Other] Clock

Description: --1.实体和函数的定义 --2.自动计时部分 --3.设置调时时的四种状态:a.不调时,b.调时位,c.调分位,d.调秒位 --4.设置闪烁的位置,调哪部分,哪部分闪烁 --5.将该闪烁的部分执行闪烁命令 --6.调时间,小时,分钟,秒的调时进程 --7.用元件BCD把小时位,分钟位和秒位三部分连接在一起 --8.设置时区***该部分为选做,程序中已经注释掉*** --9.设置闹铃***该部分为选做,程序中暂时没写*** --10.设置7段数码管的显示位置 --11.数码管显示-- 1. Entities and function definitions - 2. Automatic timing part of it - 3. Set the tone from time to time of the four states: a. not transfer, when, b. when the transfer bit, c. transfer sub-spaces, d. tone seconds bit- 4. to set the location of blinking, adjusting which part, which part of the flashing- 5. the flashing part of the implementation of the flashing command- 6. transfer time, hours, minutes, seconds, when the process of adjustment- 7 . using devices to hours-bit BCD, minutes, seconds bit and bit three parts together- 8. set the time zone*** to do that part for the election, the program has been commented out***- 9. Set alarm*** This part is selected to serve as the program for the moment I did not write***- 10. set the 7-segment digital tube display position- 11. nixie tube display
Platform: | Size: 4096 | Author: wvqyd | Hits:

[VHDL-FPGA-Verilog] wtut_edif

Description: Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
Platform: | Size: 20480 | Author: shad | Hits:

[Other] 7SegmentDigitalClock

Description: LABVIEW开发的。分７段的ＬＥＮ时钟显示，希望对你有帮助.-this is labview 7 Segment Digital Clock.
Platform: | Size: 117760 | Author: liyan | Hits:

[VHDL-FPGA-Verilog] 123654vhaing

Description: 八音自动播放电子琴设计 vhdl源码，文件内有具体注释 [VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9- -Octave electronic keyboard play automatically design vhdl source, document specific comments [VHDL-XILINX-EXAMPLE26.rar]- [VHDL design of 26 cases of classic]- in the xilinx chip debugging through- [01- 1 adder ] [02- 2 S 1 MUX] [03- 8-bit hardware adder] [04- 7-segment digital display decoder] [05- 8 bit string into and out of register] [6--8 bit string into a register] [7- internal three-state bus] [8- with clear and clock enable synchronous 4-bit adder counter] [9-
Platform: | Size: 231424 | Author: 杨领超 | Hits:

[Education soft system] 7-segment-Digital-Clock-using-Labview

Description: 7-segment BCD display. it is used to design the digital clock system.
Platform: | Size: 18432 | Author: anbu | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟， 实现分钟的增或者减。该设计包括以下几个部分： （1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲； （2）手动调节电路，包括“时增”“时减”“分增”“分减”。 （3）时分秒计时电路。 （4）7 段数码管显示电路。-Design with VHDL, digital clock, to achieve in the digital display minutes and seconds, and you can manually adjust the minutes, to achieve the increase or decrease minutes. The design includes the following sections: (1) frequency circuit design, produce 1Hz clock signal, as the second timing pulse (2) Manual adjustment circuit, including " the increase" " decrease the time" " point by" " sub- less. " (3), minute and second timing circuits. (4) 7-segment display circuit.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] led_shizhong

Description: 8位显示电子时钟，由7段数码管作为显示输出，带有调试调分调秒的按键功能-8-bit display digital clock, as the 7-segment display output, with sub-tone seconds debug button adjustment function
Platform: | Size: 4096 | Author: 应斌斌 | Hits:

[Windows Develop] fVerrilog_Devr

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL source code quite popular, she will Verilog source together with contribution to everyone: eight priority encoder, multipliers, multiplexers binary switch the BBCD code, adder, subtracter, simple straightforward state machine, four comparators, 7-segment LED, i2c bus, lcd LCD LCD display, DIP switch, serial port, buzzer, matrix keyboard, Marquee, traffic lights, digital clock can be used directly.
Platform: | Size: 3170304 | Author: qtzx | Hits:

[Other] VHDL_book1

Description: gate：基本逻辑门的实现和验证 mux4_1_gate：多路复用器的门级实现和验证 mux4_1_behav：多路复用器的行为级实现和验证 seg7_gate：7段数码管逻辑门实现和验证 seg7_behav：7段数码管case语句描述和验证 mux7seg：采用按键复用7段数码管的实现和验证 clkseg7：采用时钟自动扫描复用7段数码管的实现和验证 comp4_gate：4位比较器结构化实现和验证 comp8_behav：8位比较器行为实现和验证 decode3_8_gate：3-8译码器的逻辑门实现和验证 decode3_8_behav：3-8译码器的case语句实现和验证 encode8_3_gate：8-3编码器的门级实现和验证 encode8_3_behav：8-3编码器的逻辑门实现和验证 priority_encoder8_3： 8-3优先级编码器的循环语句实现和验证 binbcd4_gate：4位二进制码到BCD码变换设计 binbcd8_behav：8位二进制码到BCD码变换设计 bin_gray4_gate：4位二进制码到Gray码的变换设计 binbcd4_gate：4位Gray码到二进制码变换设计-gate: the realization of basic logic gates and verification mux4_1_gate: multiplexer gate-level implementation and verification mux4_1_behav: Multiplexer behavioral implementation and verification seg7_gate: 7-segment digital tube logic gate implementation and verification seg7_behav: 7 segment digital tube case statements describe and validate mux7seg: using buttons multiplex seven segment LED implementation and verification clkseg7: clock automatically scans using 7-segment digital tube multiplex implementation and verification comp4_gate: 4-bit comparator structured implementation and verification comp8_behav: 8-bit comparator behavior implementation and verification decode3_8_gate :3-8 decoder logic gate implementation and verification decode3_8_behav :3-8 decoder implementation and verification of case statement encode8_3_gate :8-3 encoder gate-level implementation and verification encode8_3_behav :8-3 encoder implementation and verification of logic gates priority_encoder8_3: 8-3
Platform: | Size: 7627776 | Author: 贾诩 | Hits:

[VHDL-FPGA-Verilog] VHDL-book3

Description: D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mod5cnt：模5计数器的设计 mod10Kcnt：时钟分频器的设计 morsea：任意波生成器的设计 sw2reg：加载开关量到寄存器的设计 shift_reg8：移位数据到移位寄存器的设计 scroll：滚动7段数码显示设计 fib：Fibonacci序列设计 pwm4：PWM控制直流电机设计 pwmg：PWM控制伺服电机位置设计-D_flipflop: 1-bit D flip-flop design D_fllipflop_behav: 4-bit D flip-flop design reg1bit: 1-bit register design reg4bit: 4-bit register design shiftreg4: general shift register design ring_shiftreg4: ring shift register design debounce4: elimination shake circuit design clock_pulse: clock pulse circuit design count3bit_gate: 3-bit counter design count3bit_behav: 3-bit counter design mod5cnt: Mode 5 counter design mod10Kcnt: clock divider design morsea: arbitrary waveform generator design sw2reg: Load switch to register the design shift_reg8: shift data into the shift register design scroll: Scroll 7-segment digital display design fib: Fibonacci Sequence Design pwm4: PWM controlled DC motor design pwmg: PWM servo motor position control design
Platform: | Size: 9017344 | Author: 贾诩 | Hits:

[SCM] shuzishizhong

Description: 电子钟在生活中应用非常广泛，而一种简单方便的数字电子钟则更能受到人们的欢迎。所以设计一个简易数字电子钟很有必要。本电子钟采用ATMEL公司的AT89S52单片机为核心，使用12MHz 晶振与单片机AT89S52 相连接,通过软件编程的方法实现以24小时为一个周期，同时8位7段LED数码-Electronic clock is widely used in life, and a simple and convenient digital clock is more welcomed by the people. So designing a simple digital clock is necessary. The electronic clock uses ATMEL Corporation AT89S52 microcontroller as the core, using 12MHz crystal is connected with the microcontroller AT89S52 through software programming method to achieve a 24-hour cycle, while eight 7-segment LED
Platform: | Size: 56320 | Author: 林卫东 | Hits:

[VHDL-FPGA-Verilog] Lab15_sw2reg

Description: 开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。-Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.
Platform: | Size: 175104 | Author: penglx1803 | Hits:

[Other Embeded program] segclk2

Description: digital clock using 7 segment display
Platform: | Size: 41984 | Author: balu | Hits:

[Other Embeded program] PIC-16F84-12-24-Hour-Digital-Clock-hex-and-asm-fi

Description: PIC16F84 12 or 24 Hour Digital Clock Circuit Diagram And Programming --------------------------------------------------- This PIC digital clock is based on a 16F84 microcontroller. it uses four 7-segment displays.The software in the microcontroller allows for very accurate timekeeping. -PIC16F84 12 or 24 Hour Digital Clock Circuit Diagram And Programming --------------------------------------------------- This PIC digital clock is based on a 16F84 microcontroller. it uses four 7-segment displays.The software in the microcontroller allows for very accurate timekeeping. ----------------------------------------------------
Platform: | Size: 93184 | Author: Daniel H | Hits:

[LabView] shuzizhong

Description: 采用LabVIEW编写的数字钟！除一般功能外还可以显示生肖图片、调节颜色等等！另外，采用Xcontrol编写的7段码显示控件也很有特色！-LabVIEW prepared using a digital clock! In addition to the general functions can also display the zodiac picture, adjust color, and so on! In addition, the 7-segment display controls written using Xcontrol also very unique!
Platform: | Size: 3235840 | Author: 宋威 | Hits:

[Other] digital_clk

Description: VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
Platform: | Size: 950272 | Author: Casey | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟， 实现分钟的增或者减。该设计包括以下几个部分： （1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲； （2）手动调节电路，包括“时增”“时减”“分增”“分减”。 （3）时分秒计时电路。 （4）7 段数码管显示电路。 将 SW1 和SW2 初始状态均置为高电平。拨动开关SW1 到低，分钟进行加计数，秒停 止计数，当计数到59 时，从00 开始重新加计数，将SW1 拨动到高时，在当前状态进行计时。当拨动开关SW2 为低时，分钟进行减计数，秒停止计数，当减到0 时，从59 开始减计数，将SW2 拨动到高时，在当前状态进行计时。-VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes, To achieve the increase or decrease minutes. The design includes the following sections: (1) frequency circuit design, resulting in 1Hz clock signal, as the second time pulse (2) manual adjustment of the circuit, including when the increase when the minus points by sub-minus. (3) when the minutes and seconds timer circuit. (4) 7-segment LED display circuit. Set the initial state of SW1 and SW2 to high level. Toggle switch SW1 to low, minute to count up, seconds to stop Stop counting, when counting to 59, 00 to re-count the start, will SW1 toggle to high, in the current state of time. When the switch SW2 is low, the timer counts down in minutes and stops counting in seconds. When it decreases to 0, it counts down 59, and turns SW2 to HIGH to count in the current state.
Platform: | Size: 495616 | Author: panda | Hits:
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